1. Field of the Invention
This invention pertains to semiconductor integrated circuits, and more specifically to the effecting of a reliable buried contact between the gate of a transistor device and a diffusion area separated from the transistor device. The invention has particular applicability to integrated circuits for use in memory and logic cells.
2. Background Art
The trend in semiconductor integrated circuitry continues to involve a decrease in the size of individual semiconductor structures accompanied by an increase in the complexity and number of such structures aggregated on a single semiconductor integrated chip. Single semiconductor devices have been grouped into integrated circuits, which in turn have been further densified into large scale integrated semiconductor systems. Structural flaws which previously passed unnoticed in individual semiconductor devices and integrated semiconductor circuit systems have become significant, debilitating structural shortcomings in intensely miniaturized, densely packed large scale integration efforts.
In memory cells and in logic cells, for example, it has been common to interconnect the gate of a transistor device through the surface of the semiconductor substrate upon which it is located to various diffusion areas formed in the surface of that substrate at locations remote from the transistor device itself. The problems inherent in accomplishing this objective are numerous, but such problems become more prominent as the semiconductor devices involved are rendered in progressively smaller scale and in increasingly densified arrangements with other devices.
An example of such a typical memory cell is shown schematically in FIG. 1 as comprising a pair of transistors T.sub.1 and T.sub.2 each series connected with a respective biasing resistor R.sub.1 and R.sub.2 between a bias voltage V.sup.+ and ground. Transistor T.sub.1 comprises a source S.sub.1, a drain D.sub.1, and a gate G.sub.1 therebetween for governing current flow through transistor T.sub.1. Correspondingly, transistor T.sub.2 comprises a source S.sub.2, a drain D.sub.2, and a gate G.sub.2 located therebetween.
Typically a transistor device, such as T.sub.1 or T.sub.2, is formed at the surface of a semiconductor substrate so as to assume in elevation a cross-sectional structure such as that shown in FIG. 2. There it can be seen that the elements of transistor T.sub.1 are located on a substrate 12 at a p-type conductivity well 14 formed in the surface 16 thereof. The gate G.sub.1 of transistor T.sub.1 comprises a polysilicon gate layer 18 having a top surface 19 and being disposed on a gate insulator 20 on surface 16 of substrate 12. Typically gate insulator 20 is formed of silicon dioxide. To either side of gate G.sub.1 are formed n+ diffusion regions 22, 24 which function as the source S.sub.1 and the drain D.sub.1 of transistor T.sub.1, respectively.
The elements of transistor T.sub.1 are electrically isolated from the balance of substrate 12 by the combination of relatively thick, surrounding oxide barriers 26 on surface 16 of substrate 12 and p-type conductivity well 14 formed therein. Conductivity well 14 must, therefore, extend deep enough into substrate 12 from surface 16 thereof to prevent the electrical current that passes through the elements of transistor T.sub.1 from leaking out of conductivity well 14 into substrate 12. Nevertheless, the evolution of large scale integrated circuitry imposes on circuit designs an imperative for shallower conductivity wells.
Leakage currents degrade seriously the ability of any semiconductor device, such as transistor T.sub.1, to function in the manner intended. The consequences of excessive leakage currents in the context of memory and logic cells are a concern and will be discussed subsequently. First, however, the cause of leakage currents, as well as some other related dysfunctionalities, will be explored relative to manufacturing a buried contact between a gate of a transistor device, such as gate G.sub.1, and a diffusion region formed in the surface of a semiconductor substrate remote therefrom.
It is common in configuring a pair of transistors into a memory cell, such as transistors T.sub.1 and T.sub.2 in FIG. 1, to cross-couple the gate of one transistor to the source of the other. Thus, as seen in FIG. 1, gate G.sub.1 of transistor T.sub.1 is coupled through a current path 28 to the diffusion region which functions as the drain D.sub.2 of transistor T.sub.2. Similarly, gate G.sub.2 of transistor T.sub.2 is coupled by another current pathway 30 to the diffusion region which functions as the drain D.sub.1 of transistor T.sub.1.
Current pathways 28 and 30 are generally not formed through the top surface 19 of a gate layer 18, but rather through other portions of the gate structure. The current pathway is thus buried in the structures of the semiconductor device surrounding and underlying the gate layer 18, ensuring electrical isolation from other circuit paths and leaving the top surface 19 of gate layer 18 free for other interconnections. The cause of leakage currents and of other selected structural shortcomings associated with buried contacts, such as current pathways 28, 30, will best be understood through a brief exploration of a typical manner in which such buried contacts are actually fabricated. This will be explained using the sequence of drawings comprising FIGS. 3A through 3E.
In FIG. 3A, a thin insulative layer 32 of silicon oxide has been grown on surface 16 of substrate 12 at p-type conductivity well 14. Through subsequent processing, insulative layer 32 will be formed into a gate insulator, such as gate insulator 20 shown in FIG. 2. Toward this end, a photo-resist mask 34 is formed over the entirety of insulative layer 32, and an opening 36 is developed therein. Thereafter, insulative layer 32 is etched from surface 16 of substrate 12 through opening 36.
As shown in FIG. 3B, this etching process isolates from insulative layer 32 by a separation distance 38 a portion thereof which will ultimately function as gate insulator 20. A thick polysilicon layer 40 is then deposited over insulative layer 32 and gate insulator 20, as well as over the portion of surface 16 of substrate 12 exposed in separation 38 therebetween. Through subsequent etching yet to be described, polysilicon layer 40 is intended to be fashioned into the gate, such as gate layer 18 shown in FIG. 2, of a transistor device. In addition, however, a portion of gate layer 18 will be connected by a current pathway, such as current pathway 28, to a diffusion region formed in substrate 12 remote from gate layer 18.
Toward this end, in FIG. 3B a second photo-resist mask 42 is formed over polysilicon layer 40 and developed so as to terminate over separation 38. The portion of polysilicon layer 40 unprotected by second photo-resist mask 42 is then removed by dry etching. Because of the thickness of polysilicon layer 40 and the need to insure its total removal in the areas not covered by second photo-resist mask 42, over etching is called for. Insulative layer 32 is exposed by the removal of polysilicon layer 40 and resists further etching. Nevertheless at the surface 16 of substrate 12 that is not protected by insulative layer 32 or second photo-resist mask 42, the removal of material by etching continues, creating a relatively deep trench 44 (FIG. 3C).
The portion of polysilicon layer 40 remaining following this etching comprises gate layer 18 which, for example, can function with gate insulation 20 as the gate G.sub.1 of a transistor T.sub.1, such as shown in FIG. 1. As seen in FIG. 3B, however, second photo-resist mask 42 overlies a portion of polysilicon layer 40 filling separation distance 38 between gate insulator 20 and insulative layer 32. Then as understood from FIG. 3C, the dry etching leaves at the edge of gate layer 18 adjacent to separation distance 38 a portion of polysilicon layer 40 that contacts surface 16 of substrate 12 between trench 44 and the side edge 52 of gate insulator 20 opposite therefrom. This portion of polysilicon layer 40 is integral with gate layer 18 and will be referred to hereinafter as extension 50 thereof.
Thereafter as shown in FIG. 3D, by suitable deposition and patterning techniques, an electrically insulating oxide layer 54 is created that covers a portion 65 of the floor 46 of trench 44 and the side edge 56 of gate layer 18 at extension 50 thereof. Using oxide layer 54 as a mask, n.sup.+ -type ions are implanted in the portion of floor 46 of trench 44 not covered by oxide layer 54, forming thereat an n.sup.+ -type ion implant region 58.
The structure illustrated in FIG. 3D is then subjected to heat treatment, whereupon the n.sup.+ -type ions in n.sup.+ region 58 diffuse into p-type conductivity well 14 to form an n.sup.+ -type diffusion region 60 remote from gate layer 18. N.sup.+ -type diffusion region 60 corresponds, for example, to the diffusion region constituting drain D.sub.2 of transistor T.sub.2 in FIG. 1. During the same heat treatment, n.sup.+ -type ions from the polysilicon in gate layer 18 migrate across the portion of surface 16 of substrate 12 contacted by extension 50 of gate layer 18 forming n.sup.+ -type migration region 62. Migration region 62 extends downwardly into conductivity well 14, as well as laterally beneath gate insulator 20 and, in the opposite direction therefrom, beneath oxide layer 54 and trench 44 to make contact with the side of n.sup.+ -type ion implant region 60.
In this manner, a current pathway illustrated in FIG. 3E arrows I.sub.1, is established between gate layer 18 and n.sup.+ -type diffusion region 60. Current pathway I corresponds, for example to a current pathway, such as current pathway 28 shown in FIG. 1, between gate G.sub.1 of transistor T.sub.1 and drain D.sub.2 of transistor T.sub.2. As current pathway I.sub.1 does not pass through top surface 63 of gate layer 18, the contact structure through which current pathway I.sub.1 is established is referred to as being buried.
To facilitate future discussions, the bracketed portion of surface 16 of substrate 12 contacted by extension 50 of gate layer 18 will be referred to hereinafter as the surface current pathway interface 64 for the buried contact illustrated Similarly, the region of contact between the sides of n.sup.+ -type migration region 62 and n.sup.+ -type diffusion region 60 will be referred to hereinafter as the buried current pathway interface 66 of the buried contact illustrated.
Several problems have become apparent in the structure of a buried contact, such as that illustrated in FIG. 3E. First, due to the depth to which trench 44 penetrates surface 16 of substrate 12, the size of buried current pathway interface 66 is extremely small. In some instances, contact between n.sup.+ -type migration region 62 and n.sup.+ -type diffusion region 60 is not even effected, as where trench 44 is simply too deep, or where the number of n.sup.+ -type ions available for migration from ion implant region 62 and gate layer 18 are relatively few. The failure of n.sup.+ -type migration region 62 to make contact with -type diffusion region 60 can also result when the duration of the heating used to induce the migration of n.sup.+ -type ions is too short. The result of a small or ineffective buried current pathway interface 66, however, is an undesirably high resistance to the passage of current along the current path I.sub.1. This imposes the need for compensating alterations in other elements of the circuitry.
Another disadvantage of the type of buried contact illustrated in FIG. 3E is the leakage of current out of n.sup.+ -type regions 60, 62. The deep penetration of trench 44 into surface 16 of substrate 12, alone or in combination with the high resistance created at the relatively small buried current pathway interface 66, contributes to the divergence of current passing along current pathway I.sub.1 from its intended route into p-type conductivity well 14 and through boundary 48 into substrate 12.
Such leakage current can result in the SRAM cell becoming unstable and switching from one state to another. Again, engineering changes in other aspects of the configuration, such as the deepening of the n.sup.+ -type regions 60, 62, can be utilized to combat this phenomenon, but these are undesirable, particularly in a design environment in which miniaturization and component density are to be increased. The problem of leakage current is particularly acute where buried contacts of the type illustrated are employed with semiconductor devices used in computer memory cells. To counteract such leakage current, a higher resistor current is required resulting in increased power consumption. Where the device employing the memory cell is battery operated, that battery must be larger than would otherwise be required.
The sequence of processing steps by which the buried contact illustrated in FIG. 3E is manufactured lead to other disadvantages. For example, in the shaping of insulative layer 32 into gate insulator 20 it is necessary to dispose a photo-resist mask 34 (see FIG. 3A) directly upon that portion of insulative layer 32 which ultimately will become gate insulator 20. In the process, contaminants from photo-resist mask mask 34 enter insulator layer 32 and migrate therefrom in the heating process by which diffusion region 60 and migration region 62 are subsequently created. The migration of such contaminants out of gate insulator 20 electrically weakens gate insulator 20 in its intended function of electrically isolating gate layer 18 from surface 16 of substrate 14. Ion contamination from gate insulator 20 tends to migrate to the oxide-silicon interface at surface 16 of substrate 12. There the contaminants interfere with the establishment of the desired threshold voltages for the resultant overall device. This is particularly troublesome with respect to the turn-on voltages when a transistor device with a buried contact such as that illustrated in FIG. 3E is used, for example, in the context of a memory or logic cell.